The present invention relates generally to semiconductor integrated circuit devices. More particularly, the present invention relates to integrated circuit devices containing both memory and logic on the same integrated circuit, and also to the methods for manufacturing such integrated circuit devices.
It is generally desirable in chip fabrication to provide both logic and memory circuitry on the same integrated circuit chip. An example of such memory circuitry is a dynamic random access memory (DRAM) device. A three device cell DRAM is not very attractive for stand alone memory applications due to area requirements. However, for embedded applications, the three device cell provides an attractive approach because of process integration considerations. DRAMs offer the advantage of increased memory for device size. For example, they are favored over static random access memory (SRAM) devices because SRAMs require a relatively large number of transistors. In contrast, DRAMs require less space. The drawback of DRAM technology is, however, that DRAM devices (unlike SRAMs) require periodic replenishment of the charge in their circuitry to function as memory devices. DRAMs store memory in the form of charge stored on a capacitor. The stored charge is prone to leakage and other forms of dissipation and, therefore, must be replenished on a regular basis. The amount of charge stored for a given capacitor is proportional to the size of the electrodes which form the capacitor.
Modern technology has developed VLSI (very-large-scale integration) procedures for device design and manufacture. As technology progresses, the ability to reliably and repeatably produce increasingly smaller device features increases. Device sizes shrink, which results in more devices for a given substrate size, which increases cost efficiency, because the cost of a substrate and the cost to process a substrate through a process operation is fixed. Another advantage of the advancing miniaturization is that more memory can be built into a device of a given size. So, the general challenge is to build a device which is as small as possible and which contains as much memory as possible.
Therefore, for DRAM devices, it is desirable to store as much charge as possible using the smallest device geometry possible. A device which relies solely on parasitic capacitance (which is the ability of a transistor gate to store charge itself, without a separate storage capacitor) cannot store a great amount of charge. Therefore, it is desirable to provide increased capacitance for a given cell. A typical cell of an embedded DRAM device may consist of three transistor devices and a storage node capacitor. The size of the charge storage node of a capacitor in an embedded DRAM device becomes important because the charge storage capacity of a given capacitor is proportional to the size of the electrodes which form the capacitor.
The technology for producing DRAM devices is understood to be limited by the amount of charge which may be stored for a given size. It is desirable to have the storage node capacitor store as much charge as possible for a given amount of device surface area, and to store as much charge as possible per transistor, because the transistors and the capacitor compete for the same surface space within the memory cell that they combine to form. Thus, it is desirable to integrate as much capacitance as possible into the smallest, most highly integrated device cell as possible. One way to accomplish this is to use features of other components within the cell to form the charge-storing capacitor. This technique maximizes the integration of the cell. One conventional approach to achieve this technique is to integrate vertically by building capacitors on top of other components of the cell. A capacitor so built is called a stacked capacitor. Although the prior art provides a structure for a stacked capacitor, it does so at the expense of increased process complexity.
Storage capacitors exist in which one feature of the transistor components also serves as a portion of the capacitor or in which an interconnect layer between the components forms part of the capacitor. A cell with a stacked capacitor has a capacitor that is stacked above other components of the cell, in this particular case, over portions of the three transistors. Although the prior art structures may incorporate one feature of the existing transistor structure to form a part of a stacked capacitor, however, additional processing is required to complete the capacitor structure. As technology improvements allow for increasingly smaller device components and provide for higher degrees of integration, there is an increased challenge to incorporate other features of the transistors into the capacitor storage structure.
In the manufacture of semiconductor integrated circuit devices, it is also desirable to build a completed device using the fewest number of process operations. Fewer processing operations allows the devices to be built more quickly and less expensively, because each individual process operation requires raw materials and manpower to complete. Fewer process operations also reduce the number of devices lost due to contamination and reduce the chance for scrap due to misprocessing at a process operation. The use of fewer processing layers also provides benefits from a device perspective, in addition to the above advantages. The use of fewer layers or films decreases the risk of progressive misalignment of one device layer to another layer which is several layers removed. Fewer films used to make a device also results in fewer issues regarding the conformality of one film over another.
The manufacturing process for fabricating stacked capacitor devices typically involves fabricating the transistor components first. This involves introducing an impurity region into the semiconductor substrate, usually by a diffusion or ion implantation process, and also involves depositing and patterning of a semiconductor film to produce transistors. Then, following those operations, the stacked capacitors are fabricated physically on top of the previously formed transistors. A capacitor stores charge by the use of two electrodes. Capacitors in the existing art are comprised of electrodes made of semiconductor films added after the formation of the transistors. Thus, the capacitors are formed of semiconductor films other than the semiconductor film which forms the gates of the transistors. Although the stacked capacitor technology may involve the use of one or both of these electrodes as an interconnect material, the prior art does not involve using part of an impurity region of a functioning transistor to form one of the electrodes of the capacitor.
The deficiencies of the conventional stacked capacitor devices show that a need still exists for an improved device that provides both logic and memory circuitry on the same integrated circuit chip. To overcome the shortcomings of the conventional devices and methods of manufacturing those devices, a new stacked capacitor device is provided. An object of the present invention is to manufacture a device where the charge storing ability of the circuitry is maximized. As such, a related object is to build a device which is as small as possible and which contains as much memory as possible. Still another object of the present invention is to use features of other components within the cell to form the charge-storing capacitor. A further object is to build a completed device using the fewest number of process operations. A related object is to use fewer processing layers, thereby decreasing both the risk of progressive misalignment of one device layer to another layer and the number of issues regarding the conformality of one layer over another. An additional object is to manufacture a device that uses part of the functioning transistor component to form one of the electrodes of the capacitor.
To achieve these and other objects, and in view of its purposes, the present invention provides an improvement to the stacked capacitor technology existing in the current art. The improvement consists of adding a capacitor to a DRAM memory cell without adding process complexity. The same processes used to form and connect the memory transistors also form the capacitor. Specifically, the present invention involves the fabrication of a three device DRAM memory cell with a storage capacitor which is fabricated using only two layers of a deposited semiconductor film. A source/drain impurity region of one of the transistors, which is created within the main surface of the semiconductor substrate, forms one of the electrodes of the storage capacitor.
The first deposited semiconductor film forms the gates of the transistors. The second deposited semiconductor film connects a gate of one transistor with the source/drain impurity region of another and forms the other electrode of the capacitor. The second deposited semiconductor film may also connect the cell to other cells or devices within the integrated circuit. Thus, an additional semiconductor film to form one electrode, and the dielectric film to isolate this semiconductor film from the transistors below, are not required. Nor are the associated patterning or planarizing processes associated with these films required. The invention offers the advantages which result from an improved storage capacitance over cells which use only parasitic capacitance, and a reduced number of processing operations compared to stacked capacitors.
The present invention also maximizes the degree of integration and the amount of charge stored both per substrate area (because the capacitor uses an existing transistor impurity region and requires less lateral area) and per associated transistor. The three transistors forming the cell may be integrated into a small surface area. The design maximizes the efficient use of cell space; the capacitor sits atop the source/drain region of one transistor and connects to the gate of another transistor.